MC68HC705P6A Datasheet, PDF (59/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Advance Information — MC68HC705P6A
Section 7. Serial Input/Output Port (SIOP)
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .62
7.4.2 SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .63
7.4.3 SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or
other MCUs. The SIOP is implemented as a 3-wire master/slave system
with serial clock (SCK), serial data input (SDI), and serial data output
(SDO). A block diagram of the SIOP is shown in Figure 7-1. A mask
programmable option determines whether the SIOP is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B DDR and data
registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could
affect the transmitted or received data.
MC68HC705P6A — Rev. 2.0
MOTOROLA
Serial Input/Output Port (SIOP)
Advance Information
59