MC68HC705P6A Datasheet, PDF (97/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Central Processor Unit (CPU) Core
Registers
operand address by adding the index register contents to a 16-bit
immediate value.
The index register can also serve as an auxiliary accumulator for
temporary storage. The index register is unaffected by a reset of the
device.
12.3.3 Stack Pointer
The stack pointer shown in Figure 12-1 is a 16-bit register internally. In
devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The stack pointer contains the address
of the next free location on the stack. During a reset or the reset stack
pointer (RSP) instruction, the stack pointer is set to $00FF. The stack
pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the 10 most significant bits are permanently
set to 0000000011. The six least significant register bits are appended
to these 10 fixed bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 ($40) locations.
If 64 locations are exceeded, the stack pointer wraps around and writes
over the previously stored information. A subroutine call occupies two
locations on the stack and an interrupt uses five locations.
12.3.4 Program Counter
The program counter shown in Figure 12-1 is a 16-bit register internally.
In devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The program counter contains the
address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
MC68HC705P6A — Rev. 2.0
MOTOROLA
Central Processor Unit (CPU) Core
Advance Information
97