MC68HC705P6A Datasheet, PDF (72/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Capture/Compare Timer
8.4.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5,
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes ATRL to be latched until ATRL is
read. Reading ATRL has no effect on the timer overflow flag (TOF).
Writing to the alternate timer registers has no effect.
Address: ATRH — $001A
Bit 7
6
Read: ACRH7 ACRH6
Write:
Reset: 1
1
5
ACRH5
1
4
ACRH4
1
3
ACRH3
1
2
ACRH2
1
1
ACRH1
1
Bit 0
ACRH0
1
Address: ATRL — $001B
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE:
To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.
Advance Information
72
Capture/Compare Timer
MC68HC705P6A — Rev. 2.0
MOTOROLA