MC68HC705P6A Datasheet, PDF (62/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Input/Output Port (SIOP)
7.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
7.4.1 SIOP Control Register (SCR)
This register is located at address $000A and contains two bits. Figure
7-3 shows the position of each bit in the register and indicates the value
of each bit after reset.
Address: $000A
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
SPE
MSTR
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP
control register while a transmission is in progress will cause the SPIF
and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written
once to enable the SIOP and then not written to until the SIOP is to
be disabled. Clearing the SPE bit while a transmission is in progress
Advance Information
62
Serial Input/Output Port (SIOP)
MC68HC705P6A — Rev. 2.0
MOTOROLA