MC68HC705P6A Datasheet, PDF (74/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Capture/Compare Timer
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
Address: OCRH — $0016
Bit 7
6
5
4
3
2
1
Bit 0
Write:
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
Read:
Unaffected by reset
Address: OCRL — $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
Advance Information
74
Capture/Compare Timer
MC68HC705P6A — Rev. 2.0
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