MC68HC705P6A Datasheet, PDF (42/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets
4.3 External Reset (RESET)
The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in Section 14. Electrical Specifications.
4.4 Internal Resets
The two internally generated resets are the initial power-on reset (POR)
function and the computer operating properly (COP) watchdog timer
function.
4.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal clock cycle oscillator stabilization delay after the oscillator
becomes active.
The POR will generate the RST signal and reset the MCU. If any other
reset function is active at the end of this 4064 internal clock cycle delay,
the RST signal will remain active until the other reset condition(s) end.
4.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set),
the internal COP reset is generated automatically by a timeout of the
COP watchdog timer. This timer is implemented with an 18-stage ripple
counter that provides a timeout period of 65.5 ms when a 4-MHz
oscillator is used. The COP watchdog counter is cleared by writing a
logical 0 to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the
MOR or by applying 2 x V_DD to the IRQ/V_PP pin (for example, during
bootloader). When the IRQ/V_PP pin is returned to its normal operating
Advance Information
MC68HC705P6A — Rev. 2.0
42
Resets
MOTOROLA