MC68HC705P6A Datasheet, PDF (73/130 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Capture/Compare Timer
Timer I/O Registers
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.
Address: ICRH — $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
Write:
Unaffected by reset
Address: ICRL — $0015
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.
MC68HC705P6A — Rev. 2.0
MOTOROLA
Capture/Compare Timer
Advance Information
73