MC9328MX21 Datasheet, PDF (92/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
hclk
hselm_weim_cs[2]
htrans
Non
seq
hwrite _Read
haddr
V1
hready
weim_hrdata
Last Valid Data
weim_hready
BCLK
A[24:0]
Last Valid
Addr
CS[2]
R/W
LBA
OE
EB (EBC=0)
EB (EBC=1)
ECB
DATA_IN
Seq
Read
V2
V1 Word
Idle
V2 Word
Address V1
Read
V1 1/2 V1 2/2 V2 1/2
V2 2/2
Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
3.20 DTACK Mode Memory Access Timing Diagrams
When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK
enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not
terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the
internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to
7.7 µs. Refer to the Section 3.5, “DPLL Timing Specifications,” on page 18 for more information on how
to generate different HCLK frequencies.
MC9328MX21 Product Preview, Rev. 1.1
92
Freescale Semiconductor