MC9328MX21 Datasheet, PDF (48/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 28. PWM Output Timing Parameter Table (Continued)
Ref
No.
Parameter
4a Output delay time¹
4b Output setup time¹
1. C_L of PWMO = 30 pF
1.8V +/- 0.10V
Minimum
9.37
8.71
Maximum
–
–
3.0V +/- 0.30V
Unit
Minimum
Maximum
3.61
–
ns
3.03
–
ns
3.15 SDRAM Memory Controller
The following figures (Figure 38 through Figure 41 on page 52) and their associated tables specify the
timings related to the SDRAMC module in the i.MX21.
1
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
DQM
3S
3H
3S
3H
3S
3H
3S
3H
2
3
4S 4H
ROW/BA
COL/BA
8
5
3S
6
Data
7
3H
Note: CKE is high during the read/write cycle.
Figure 38. SDRAM Read Cycle Timing Diagram
MC9328MX21 Product Preview, Rev. 1.1
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Freescale Semiconductor