MC9328MX21 Datasheet, PDF (56/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 32. SSI to SAP Ports Timing Parameter Table (Continued)
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
27b (Tx) CK high to STXD low
28 (Tx) CK high to STXD high impedance
29 SRXD setup time before (Rx) CK low
30 SRXD hole time after (Rx) CK low
10.80
19.36
7.71
12.08
19.36
7.71
0.37
–
0.42
0
–
0
9.20
ns
9.20
ns
–
ns
–
ns
Synchronous Internal Clock Operation (SAP Ports)
31 SRXD setup before (Tx) CK falling
32 SRXD hold after (Tx) CK falling
23.00
–
21.41
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (SAP Ports)
33 SRXD setup before (Tx) CK falling
1.20
–
0.88
–
ns
34 SRXD hold after (Tx) CK falling
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 33. SSI to SSI1 Ports Timing Parameter Table
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1 (Tx/Rx) CK clock period¹
2 (Tx) CK high to FS (bl) high
3 (Rx) CK high to FS (bl) high
4 (Tx) CK high to FS (bl) low
5 (Rx) CK high to FS (bl) low
6 (Tx) CK high to FS (wl) high
7 (Rx) CK high to FS (wl) high
8 (Tx) CK high to FS (wl) low
9 (Rx) CK high to FS (wl) low
Internal Clock Operation¹ (SSI1 Ports)
90.91
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
–
-0.15
-0.27
-0.15
-0.27
-0.15
-0.27
-0.15
-0.27
90.91
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
-0.68
-0.96
–
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
-0.15
ns
-0.27
ns
MC9328MX21 Product Preview, Rev. 1.1
56
Freescale Semiconductor