MC9328MX21 Datasheet, PDF (38/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 24. SDHC Bus Timing Parameter Table (Continued)
Ref
No.
Parameter
5a Input hold time³â€”10/30 cards
5b Input setup time³â€”10/30 cards
6a Output hold time³â€”10/30 cards
6b Output setup time³â€”10/30 cards
7 Output delay time³
1. C_L ≤ 100 pF / 250 pF (10/30 cards)
2. C_L ≤ 250 pF (21 cards)
3. C_L ≤ 25 pF (1 card)
1.8V +/- 0.10V
Min
Max
5.7/5.7
–
5.7/5.7
–
5.7/5.7
–
5.7/5.7
–
0
16
3.0V +/- 0.30V
Unit
Min Max
5/5
–
ns
5/5
–
ns
5/5
–
ns
5/5
–
ns
0
14
ns
3.12.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly N_ID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 26. The symbols for Figure 26 through
Figure 30 are defined in Table 25.
Table 25. State Signal Parameters for Figure 26 through Figure 30
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
D
Data bits
T
*
Repetition
P
CRC Cyclic redundancy check bits (7 bits)
E
Start bit (0)
Transmitter bit
(Host = 1, Card = 0)
One-cycle pull-up (1)
End bit (1)
MC9328MX21 Product Preview, Rev. 1.1
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Freescale Semiconductor