MC9328MX21 Datasheet, PDF (8/106 Pages) Motorola, Inc – i.MX family of microprocessors

Signal Descriptions
Signal Name
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
LD [17:0]
FLM_VSYNC
(or simply referred
to as VSYNC)
LP_HSYNC (or simply
referred to as HSYNC)
LSCLK
OE_ACD
CONTRAST
SPL_SPR
PS
CLS
REV
SLCDC1_CLK
SLCDC1_CS
SLCDC1_RS
SLCDC1_D0
Table 2. i.MX21 Signal Descriptions (Continued)
Function/Notes
CMOS Sensor Interface
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Controller
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals
are multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is
multiplexed with BMI_WRITE of BMI. LD[16] signal is multiplexed with BMI_READ_REQ of BMI
and EXT_DMAGRANT signals.
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with
BMI_RXF_FULL and BMI_WAIT of the BMI.
Line Pulse or HSync
Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.
Alternate Crystal Direction/Output Enable.
This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed
with the BMI_READ from BMI.
Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed
with the SLCDC1_CS.
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated
signal). This signal is multiplexed with the SLCDC1_RS.
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal
is multiplexed with SLCDC1_D0.
Smart LCD Controller
SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These
are SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.
SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are PS and SD2_CMD signals of LCDC and SD2, respectively.
SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.
SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is
inactive when a parallel data interface is used.
MC9328MX21 Product Preview, Rev. 1.1
8
Freescale Semiconductor