MC9328MX21 Datasheet, PDF (39/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Host Command
CMD S T Content CRC E Z
N_ID cycles
CID/OCR
******
Z S T Content Z Z Z
Identification Timing
Host Command
N_CR cycles
CID/OCR
CMD _{S T} Content CRC _{E Z} ******
Z S T Content Z Z Z
SET_RCA Timing
Figure 26. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 27
on page 39, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by
a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by
the responding card. The other two diagrams show the separating periods N_RC and N_CC.
Host Command
N_CR cycles
Response
CMD S T Content CRC E Z Z P ****** P S T Content CRC E Z Z Z
Command response timing (data transfer mode)
CMD S T
Response
N_RC cycles
Host Command
Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
Host Command
N_CC cycles
Host Command
CMD S T Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 27. Timing Diagrams at Data Transfer Mode
Figure 28 on page 40 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay N_AC,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance N_AC until the card sees a stop transmission command.
The data stops two clock cycles after the end bit of the stop command.
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
39