MC9328MX21 Datasheet, PDF (7/106 Pages) Motorola, Inc – i.MX family of microprocessors

Signal Name
EXTAL26M
XTAL26M
EXTAL32K
XTAL32K
CLKO
EXT_48M
EXT_266M
RESET_IN
RESET_OUT
POR
CLKMODE[1:0]
OSC26M_TEST
TEST_WB[2:0]
TEST_WB[4:3]
WKGD
TRST
TDO
TDI
TCK
TMS
JTAG_CTRL
RTCK
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Function/Notes
Clocks and Resets
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
Oscillator output to external crystal
32 kHz crystal input
Oscillator output to 32 kHz crystal
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal
clock selection.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module, SDRAMC module, and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted
from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by
an external RC circuit designed to detect a power-up event.
These are special factory test signals. To ensure proper operation, leave these signals as no
connects.
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
These are special factory test signals. However, these signals are also multiplexed with GPIO
PORT E as well as alternate keypad signals. If not utilizing these signals for GPIO functionality or
for it’s other multiplexed function, then configure as GPIO input with pull up enabled, and leave as
a no connect.
These are special factory test signals. To ensure proper operation, leave these signals as no
connects.
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising
edge of TCK.
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with OWIRE, hence utilizing OWIRE will render RTCK unusable and vice versa.
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
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