MC9328MX21 Datasheet, PDF (11/106 Pages) Motorola, Inc – i.MX family of microprocessors

Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
CSPI
CSPI1_MOSI
CSPI1_MISO
CSPI1_SS[2:0]
CSPI1_SCLK
CSPI1_RDY
CSPI2_MOSI
CSPI2_MISO
CSPI2_SS[2:0]
CSPI2_SCLK
CSPI3_MOSI
CSPI3_MISO
CSPI3_SS
CSPI3_SCLK
Master Out/Slave In signal
Master In/Slave Out signal
Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT.
Serial Clock signal
Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.
Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.
Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.
Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,
USBH2_RXDP and USBH2_RXDM signal of USB OTG
Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG
Master Out/Slave In signal. This signal is multiplexed with SD1_CMD.
Master In/Slave Out signal. This signal is multiplexed with SD1_D0.
Slave Select (Selectable polarity) signal multiplexed with SD1_D3.
Serial Clock signal. This signal is multiplexed with SD1_CLK.
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module.
TOUT1 (or simply TOUT) Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT.
TOUT2
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
TOUT3
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB_BYP
USB_PWR
USB_OC
USBG_RXDP
USBG_RXDM
USBG_TXDP
USBG_TXDM
USBG_RXDAT
USBG_OE
USB Bypass input active low signal.
USB Power output signal
USB Over current input signal
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
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