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MC9328MX21 Datasheet, PDF (34/106 Pages) Motorola, Inc – i.MX family of microprocessors | |||
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Specifications
T1
T1
VSYN
T2
HSYN
T3
XMAX
T4
T2
SCLK
Ts
LD[15:0]
Figure 22. Non-TFT Mode Panel Timing
Table 21. Non-TFT Mode Panel Timing
Symbol
Description
Minimum
Value
Unit
T1
HSYN to VSYN delay
2
HWAIT2+2
Tpix
T2
HSYN pulse width
1
T3
VSYN to SCLK
â
HWIDTH+1
Tpix
0 ⤠T3 ⤠Ts
â
T4
SCLK to HSYN
1
HWAIT1+1
Tpix
Note:
⢠Ts is the SCLK period while Tpix is the pixel clock period.
⢠VSYN, HSYN and SCLK can be programmed as active high or active low. In Figure 67 on page 83, all these 3
signals are active high.
⢠When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts.
⢠When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.
MC9328MX21 Product Preview, Rev. 1.1
34
Freescale Semiconductor
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