MC9328MX21 Datasheet, PDF (40/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z
DAT
Z****Z
Z Z P ****** P S D D D D
*****
N_AC cycles
Read Data
Timing of single block read
Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z
DAT
Z****Z
Z Z P ****** P S D D D D ***** P ***** P S D D D D *****
N_AC cycles
Read Data
N_AC cycles
Read Data
Timing of multiple block read
Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z
N_ST
DAT D D D D ***** D D D D E Z Z Z
*****
Valid Read Data
Timing of stop command
(CMD12, data transfer mode)
Figure 28. Timing Diagrams at Data Read
Figure 29 on page 41 shows the basic write operation timing. As with the read operation, after the card
response, the data transfer starts after N_WR cycles. The data is suffixed with CRC check bits to allow the
card to check for transmission errors. The card sends back the CRC check result as a CC status token on
the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a
positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured
to multiple block mode, with the flow terminated by a stop transmission command.
MC9328MX21 Product Preview, Rev. 1.1
40
Freescale Semiconductor