MC9328MX21 Datasheet, PDF (58/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 33. SSI to SSI1 Ports Timing Parameter Table (Continued)
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
32 SRXD hold after (Tx) CK falling
0
–
0
–
ns
Synchronous External Clock Operation (SSI1 Ports)
33 SRXD setup before (Tx) CK falling
2.59
–
2.28
–
ns
34 SRXD hold after (Tx) CK falling
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 34. SSI to SSI2 Ports Timing Parameter Table
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (SSI2 Ports)
1 (Tx/Rx) CK clock period¹
90.91
–
2 (Tx) CK high to FS (bl) high
0.01
0.15
3 (Rx) CK high to FS (bl) high
-0.21
0.05
4 (Tx) CK high to FS (bl) low
0.01
0.15
5 (Rx) CK high to FS (bl) low
-0.21
0.05
6 (Tx) CK high to FS (wl) high
0.01
0.15
7 (Rx) CK high to FS (wl) high
-0.21
0.05
8 (Tx) CK high to FS (wl) low
0.01
0.15
9 (Rx) CK high to FS (wl) low
-0.21
0.05
10 (Tx) CK high to STXD valid from high impedance
0.34
0.72
11a (Tx) CK high to STXD high
0.34
0.72
11b (Tx) CK high to STXD low
0.34
0.72
12 (Tx) CK high to STXD high impedance
0.34
0.48
13 SRXD setup time before (Rx) CK low
21.50
–
14 SRXD hold time after (Rx) CK low
0
–
90.91
0.01
-0.21
0.01
-0.21
0.01
-0.21
0.01
-0.21
0.34
0.34
0.34
0.34
21.50
0
–
ns
0.15
ns
0.05
ns
0.15
ns
0.05
ns
0.15
ns
0.05
ns
0.15
ns
0.05
ns
0.72
ns
0.72
ns
0.72
ns
0.48
ns
–
ns
–
ns
MC9328MX21 Product Preview, Rev. 1.1
58
Freescale Semiconductor