MC9328MX21 Datasheet, PDF (37/106 Pages) Motorola, Inc – i.MX family of microprocessors

Symbol
T1
T2
T3
T4
T5
Table 23. SLCDC Parallel Transfers Timing
Description
Minimum
Maximum
Pixel clock period
Data setup time
Data hold time
Register select setup time
Register select hold time
23
962
5
–
5
–
5
–
5
–
Specifications
Unit
ns
ns
ns
ns
ns
3.12 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
3a
3b
Bus Clock
4a
5a
CMD_DAT Input
Valid Data
12
4b
5b
Valid Data
CMD_DAT Output
7
Valid Data
Valid Data
6a
6b
Figure 25. Chip-Select Read Cycle Timing Diagram
Table 24. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1 CLK frequency at Data transfer Mode (PP)¹â€”10/30 cards
2 CLK frequency at Identification Mode²
3a Clock high time¹â€”10/30 cards
3b Clock low time¹â€”10/30 cards
4a Clock fall time¹â€”10/30 cards
4b Clock rise time¹â€”10/30 cards
1.8V +/- 0.10V
Min
0
0
6/33
15/75
–
–
Max
25/5
400
–
–
10/50 (5.00)³
14/67 (6.67)³
3.0V +/- 0.30V
Min Max
0
0
10/50
10/50
–
–
25/5
400
–
–
10/50
10/50
Unit
MHz
KHz
ns
ns
ns
ns
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
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