MC9328MX21 Datasheet, PDF (57/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 33. SSI to SSI1 Ports Timing Parameter Table (Continued)
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
10 (Tx) CK high to STXD valid from high impedance
11a (Tx) CK high to STXD high
11b (Tx) CK high to STXD low
12 (Tx) CK high to STXD high impedance
13 SRXD setup time before (Rx) CK low
14 SRXD hold time after (Rx) CK low
-1.68
-1.68
-1.68
-1.58
20.41
0
-0.36
-0.36
-0.36
-0.31
–
–
-1.68
-1.68
-1.68
-1.58
20.41
0
-0.36
ns
-0.36
ns
-0.36
ns
-0.31
ns
–
ns
–
ns
External Clock Operation (SSI1 Ports)
15 (Tx/Rx) CK clock period¹
90.91
–
16 (Tx/Rx) CK clock high period
36.36
–
17 (Tx/Rx) CK clock low period
36.36
–
18 (Tx) CK high to FS (bl) high
10.22
17.63
19 (Rx) CK high to FS (bl) high
10.79
19.67
20 (Tx) CK high to FS (bl) low
10.22
17.63
21 (Rx) CK high to FS (bl) low
10.79
19.67
22 (Tx) CK high to FS (wl) high
10.22
17.63
23 (Rx) CK high to FS (wl) high
10.79
19.67
24 (Tx) CK high to FS (wl) low
10.22
17.63
25 (Rx) CK high to FS (wl) low
10.79
19.67
26 (Tx) CK high to STXD valid from high impedance
10.05
15.75
27a (Tx) CK high to STXD high
10.00
15.63
27b (Tx) CK high to STXD low
10.00
15.63
28 (Tx) CK high to STXD high impedance
10.05
15.75
29 SRXD setup time before (Rx) CK low
0.78
–
30 SRXD hole time after (Rx) CK low
0
–
90.91
36.36
36.36
8.82
9.39
8.82
9.39
8.82
9.39
8.82
9.39
8.66
8.61
8.61
8.66
0.47
0
–
ns
–
ns
–
ns
16.24
ns
18.28
ns
16.24
ns
18.28
ns
16.24
ns
18.28
ns
16.24
ns
18.28
ns
14.36
ns
14.24
ns
14.24
ns
14.36
ns
–
ns
–
ns
Synchronous Internal Clock Operation (SSI1 Ports)
31 SRXD setup before (Tx) CK falling
19.90
–
19.90
–
ns
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
57