MC9328MX21 Datasheet, PDF (61/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 35. SSI to SSI3 Ports Timing Parameter Table (Continued)
1.8V +/- 0.10V
3.0V +/- 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
24 (Tx) CK high to FS (wl) low
9.62
17.10
7.90
15.61
ns
25 (Rx) CK high to FS (wl) low
10.30
19.54
8.58
18.05
ns
26 (Tx) CK high to STXD valid from high impedance
9.02
16.46
7.29
14.97
ns
27a (Tx) CK high to STXD high
8.48
15.32
6.75
13.83
ns
27b (Tx) CK high to STXD low
8.48
15.32
6.75
13.83
ns
28 (Tx) CK high to STXD high impedance
9.02
16.46
7.29
14.97
ns
29 SRXD setup time before (Rx) CK low
1.49
–
1.49
–
ns
30 SRXD hole time after (Rx) CK low
0
–
0
–
ns
Synchronous Internal Clock Operation (SSI3 Ports)
31 SRXD setup before (Tx) CK falling
32 SRXD hold after (Tx) CK falling
21.99
–
21.99
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (SSI3 Ports)
33 SRXD setup before (Tx) CK falling
3.80
–
3.80
–
ns
34 SRXD hold after (Tx) CK falling
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
3.17 1-Wire Interface Timing
3.17.1 Reset Sequence with Reset Pulse Presence Pulse
To begin any communications with the DS2502, it is required that an initialization procedure be issued. A
reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length
is 480 us. The bus master (one-wire) will generate this pulse, then after the DS2502 detects a rising edge
on the one-wire bus, it will wait 15-60 us before it will transmit back a presence pulse. The presence pulse
will exist for 60-240 us.
The timing diagram for this sequence is shown in Figure 46.
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
61