MC9328MX21 Datasheet, PDF (19/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
3.6 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 2 and
Figure 3 on page 20. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for
NVDD2-6 before QVDD is powered up to prevent forward biasing.
POR
1
Can be adjusted depending on the crystal
start-up time 32KHz or 32.768KHz
RESET_POR
RESET_DRAM
2
Exact 300ms
HRESET
RESET_OUT
CLK32
3
7 cycles @ CLK32
4
14 cycles @ CLK32
HCLK
Figure 2. Timing Relationship with POR
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
19