MC9328MX21 Datasheet, PDF (22/106 Pages) Motorola, Inc – i.MX family of microprocessors

Specifications
Table 11. DMA External Request and Grant Timing Parameter Table
Parameter
Description
3.0 V
WCS
BCS
1.8 V
Unit
WCS
BCS
t_{min_assert}
Minimum assertion time of
External Grant signal
8 hclk + 8.6 8 hclk + 2.74 8 hclk + 7.17 8 hclk + 3.25 ns
t_{max_req_assert}
Maximum External request
assertion time after assertion of
Grant signal
9 hclk - 20.66 9 hclk - 6.7 9 hclk - 17.96 9 hclk - 8.16 ns
t_{max_read}
Maximum External request
assertion time after first read
completion
8 hclk - 6.21 8 hclk - 0.77 8 hclk - 5.84 8 hclk - 0.66 ns
t_{max_write}
Maximum External request
3 hclk - 15.87 3 hclk - 8.83 3 hclk - 15.9 3 hclk - 9.12 ns
assertion time after completion of
first write
3.8 BMI Interface Timing Diagram
3.8.1 Connecting BMI to ATI MMD Devices
3.8.1.1 ATI MMD Devices Drive the BMI_CLK/CS
In this mode MMD_MODE_SEL bit is set and MMD_CLKOUT bit is cleared. BMI_WRITE and
BMI_CLK/CS are input signals to BMI driving by ATI MMD chip set. Output signal BMI_READ_REQ
can be used as interrupt signal to inform MMD that data is ready in BMI TxFIFO for read access. MMD
can write data to BMI RxFIFO anytime as CPU or DMA can move data out from RxFIFO much faster
than the BMI interface. Overflow interrupt is generated if RxFIFO overflow is detected. Once this
happens, the new coming data is ignored.
3.8.1.1.1 MMD Read BMI Timing
Figure 6 shows the MMD read BMI timing when the MMD drives clock.
On each rising edge of BMI_CLK/CS BMI checks the BMI_WRITE logic level to determine if the current
cycle is a read cycle. It puts data into the data bus and enables the data out on the rising edge of BMI_CLK/
CS if BMI_WRITE is logic high. The BMI_READ_REQ is negated one hclk cycle after the BMI_CLK/
CS rising edge of last data read. The MMD cannot issues read command when BMI_READ_REQ is low
(no data in TxFIFO).
MC9328MX21 Product Preview, Rev. 1.1
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Freescale Semiconductor