MC9328MX21 Datasheet, PDF (13/106 Pages) Motorola, Inc – i.MX family of microprocessors

Signal Name
SD1_D[3:0]
SD2_CMD
SD2_CLK
SD2_D[3:0]
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART3_RXD
UART3_TXD
UART3_RTS
UART3_CTS
UART4_RXD
UART4_TXD
UART4_RTS
UART4_CTS
SSI1_CLK
SSI1_TXD
SSI1_RXD
SSI1_FS
SSI1_MCLK
SSI2_CLK
SSI2_TXD
SSI2_RXD
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Function/Notes
SD Data bidirectional signals—If the system designer does not want to make use of the internal
pull-up, via the Pull-up enable register, a 50 K–69K external pull up resistor must be added.
SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO.
SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from
SLCDC1.
SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
SD Data bidirectional signals. SD2_D[3:2] are which are multiplexed with SLCDC1_RS and
SLCDC_D0 signals from SLCDC1.
UARTs – IrDA/Auto-Bauding
Receive Data input signal
Transmit Data output signal
Request to Send input signal
Clear to Send output signal
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP.
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP.
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP.
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP.
Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI.
Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI.
Request to Send input signal
Clear to Send output signal
Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP.
Transmit Data output signal which is multiplexed with USBH1_TXDM.
Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP.
Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM.
Serial Audio Port – SSI (configurable to I²S protocol and AC97)
Serial clock signal which is output in master or input in slave
Transmit serial data
Receive serial data
Frame Sync signal which is output in master and input in slave
SSI1 master clock. Multiplexed with TOUT.
Serial clock signal which is output in master or input in slave.
Transmit serial data signal
Receive serial data
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
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