MC9328MX21 Datasheet, PDF (101/106 Pages) Motorola, Inc – i.MX family of microprocessors

Table 44. Non-Gated Clock Mode Parameters (Continued)
Number
Parameter
Minimum
Maximum
5
csi_pixclk low time
6
csi_pixclk frequency
T_HCLK
0
–
HCLK / 2
Specifications
Unit
ns
MHz
HCLK = AHB System Clock
T_HCLK = Period of HCLK
3.22.3 Calculation of Pixel Clock Rise/Fall Time
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time and
setup time based on the following assumptions:
Rising-edge latch data
• max rise time allowed = (positive duty cycle - hold time)
• max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
• max rise time = (period / 2 - hold time)
• max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
• max fall time allowed = (negative duty cycle - hold time)
• max rise time allowed = (positive duty cycle - setup time)
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
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