MC68HC908RK2 Datasheet, PDF (70/232 Pages) Motorola, Inc – Microcontroller Unit

Central Processor Unit (CPU)
5.6.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
5.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
5.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Section 7. Break Module (BRK).) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
5.8 Instruction Set Summary
Table 5-1 provides a summary of the M68HC08 instruction set.
Advance Information
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Central Processor Unit (CPU)
MC68HC908RK2 — Rev. 4.0
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