MC68HC908RK2 Datasheet, PDF (179/232 Pages) Motorola, Inc – Microcontroller Unit

Input/Output (I/O) Ports
Port B
TCLK — Timer Clock
The PTB3/TCLK pin is the external clock input for TIM. The prescaler
select bits, PS[2:0], select PTB3/TCLK as the TIM clock input. (See
15.9.1 TIM Status and Control Register.) When not selected as the
TIM clock, PTB3/TCLK is available for general-purpose I/O.
MCLK — Bus Clock
The bus clock (MCLK) is driven out of pin PTB0/MCLK when enabled
by the MCLKEN bit in port B data direction register bit 7.
13.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
0
MCLKEN
Write:
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 13-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTB0. If
MCLK is enabled, PTB0 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
MC68HC908RK2 — Rev. 4.0
MOTOROLA
Input/Output (I/O) Ports
Advance Information
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