MC68HC908RK2 Datasheet, PDF (146/232 Pages) Motorola, Inc – Microcontroller Unit

Configuration Register (CONFIG)
Advance Information
146
Upon a reset, the CONFIG register defaults to predetermined settings as
shown in Figure 2-1. Memory Map.
Address: $001F
BIt 7
6
5
4
3
2
1
Read:
EXTSLOW LVISTOP LVIRST LVIPWR COPRS SSREC
Write:
STOP
Reset: 0
0
1
1
0
0
0
Figure 9-1. Configuration Register (CONFIG)
Bit 0
COPD
0
EXTSLOW — Slow External Crystal Enable Bit
The EXTSLOW bit has two functions. It configures the ICG module for
a fast (1 MHz–8 MHz) or slow (30 kHz–100 kHz) speed crystal. The
option also configures the clock monitor operation in the ICG module
to expect an external frequency higher (307.2 kHz–32 MHz) or lower
(60 Hz–307.2 kHz) than the base frequency of the internal oscillator.
(See Section 8. Internal Clock Generator Module (ICG).)
1 = ICG set for slow external crystal operation
0 = ICG set for fast external crystal operation
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWR bit is set, setting the LVISTOP bit enables the LVI
to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module.
(See Section 12. Low-Voltage Inhibit (LVI).)
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR disables the LVI module. (See Section 12. Low-Voltage
Inhibit (LVI).)
1 = LVI module power enabled
0 = LVI module power disabled
Configuration Register (CONFIG)
MC68HC908RK2 — Rev. 4.0
MOTOROLA