MC68HC908RK2 Datasheet, PDF (215/232 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
I/O Registers
CHxMAX bit takes effect in the cycle after it is set or cleared. The
output stays at 100 percent duty cycle level until the cycle after
CHxMAX is cleared.
NOTE:
The PWM 0 percent duty cycle is defined as output low all of the time.
To generate the 0 percent duty cycle, select clear output on compare
and then clear the TOVx bit (CHxMAX = 0). The PWM 100 percent duty
cycle is defined as output high all of the time. To generate the 100
percent duty cycle, use the CHxMAX bit in the TSCx register.
OVERFLOW
OVERFLOW
PERIOD
PTBx/TCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15-8. CHxMAX Latency
15.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
MC68HC908RK2 — Rev. 4.0
MOTOROLA
Timer Interface Module (TIM)
Advance Information
215