MC68HC908RK2 Datasheet, PDF (202/232 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
PTB2/TCH0
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15-3. PWM Period and Pulse Width
OUTPUT
COMPARE
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See 15.9.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50 percent.
15.5.7 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 15.5.6 Pulse-Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Advance Information
202
Timer Interface Module (TIM)
MC68HC908RK2 — Rev. 4.0
MOTOROLA