MC68HC908RK2 Datasheet, PDF (211/232 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
I/O Registers
15.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIM counter modulo registers.
Register Name and Address: TMODH—$0023
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset: 1
1
1
1
1
1
1
Bit 0
9
Bit 8
1
1
Register Name and Address: TMODL—$0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 15-6. TIM Counter Modulo Registers (TMODH and TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
15.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers (TSC0 and TSC1):
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 0 percent and 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
MC68HC908RK2 — Rev. 4.0
MOTOROLA
Timer Interface Module (TIM)
Advance Information
211