MC68HC908RK2 Datasheet, PDF (207/232 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
I/O Signals
15.8 I/O Signals
Port B shares three of its pins with the TIM. TCLK can be used as an
external clock input to the TIM prescaler and the TIM channel 0 I/O pin
PTB2/TCH0 and TIM channel 1 I/O pin PTB4/TCH1.
15.8.1 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the TIM
counter instead of the prescaled internal bus clock. Select the TCLK
input by writing logic 1s to the three prescaler select bits, PS2–PS0. See
15.9.1 TIM Status and Control Register. The minimum TCLK pulse
width, TCLK_LMIN or TCLK_HMIN, is:
1
bus frequency ^{+ tsu}
The maximum TCLK frequency is:
bus frequency ÷ 2
Refer to 16.9 Control Timing.
TCLK is available as a general-purpose I/O pin when not used as the
TIM clock input. When the TCLK pin is the TIM clock input, it is an input
regardless of the state of the DDRB3 bit in data direction register B.
15.8.2 TIM Channel I/O Pins (TCH0 and TCH1)
The channel I/O pins are programmable independently as an input
capture pin or an output compare pin. TCH0 and TCH1 can be
configured as buffered output compare or buffered PWM pins.
MC68HC908RK2 — Rev. 4.0
MOTOROLA
Timer Interface Module (TIM)
Advance Information
207