MC68HC908RK2 Datasheet, PDF (48/232 Pages) Motorola, Inc – Microcontroller Unit

FLASH 2TS Memory
7. Wait for a time, t _Kill, for the high voltages to dissipate.
8. Clear the ERASE bit.
9. After a time, t_HVD, the memory can be accessed in read mode
again.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
Table 4-2 shows the various block sizes which can be erased in one
erase operation.
BLK1
0
0
1
1
Table 4-2. Erase Block Sizes
BLK0
0
1
0
1
Block Size, Addresses Cared
Full array: 2 Kbytes
One-half array: 1 Kbytes
Eight rows: 64 bytes
Single row: 8 bytes
In step 3 of the erase operation, the cared addresses are latched and
used to determine the location of the block to be erased. For instance,
with BLK0 = BLK1 = 0, writing to any FLASH 2TS address in the range
$7800 to $78F0 will enable the erase of all FLASH memory.
4.7 FLASH 2TS Program/Margin Read Operation
NOTE:
After a total of eight program operations have been applied to a row, the
row must be erased before further programming to avoid program
disturb. An erased byte will read $00.
The FLASH 2TS memory is programmed on a page basis. A page
consists of one byte. The smart programming algorithm (Figure 4-2) is
recommended to program every page in the FLASH 2TS memory.
Advance Information
48
FLASH 2TS Memory
MC68HC908RK2 — Rev. 4.0
MOTOROLA