MC68HC908RK2 Datasheet, PDF (55/232 Pages) Motorola, Inc – Microcontroller Unit

FLASH 2TS Memory
Embedded Function Descriptions
Ready/verify
RAM optioin:
This subroutine both compares data passed in the DATA array to the
FLASH data and reads the data from FLASH into the DATA array. It also
calculates the checksum of the data.
Output to PA0 This subroutine dumps the data from the range to PA0 in the same
option: format as monitor data. It also calculates the checksum of the data.
NOTE: This serial dump does not circumvent security because the security
vectors must still be passed to make FLASH readable in monitor mode.
4.11.2 PRGRNGE Routine
Name: PRGRNGE
Purpose: Programs a range of addresses in FLASH memory
Entry conditions: H:X
Contains the first address in the range
LADDR Contains the last address in the range
DATA
Contains the data to be programmed (length is user
determined)
CPUSPD Contains the bus frequency times 4 in MHz
BUMPS Contains the maximum allowable number of programming
bumps to use
Exit conditions: C bit
Set if successful program; cleared otherwise
I bit
Set, masking interrupts
This routine programs a range of FLASH defined by H:X and LADDR.
The range can be from one byte to as much RAM as can be allocated to
DATA. The smart programming algorithm defined in 4.7 FLASH 2TS
Program/Margin Read Operation is used.
MC68HC908RK2 — Rev. 4.0
MOTOROLA
FLASH 2TS Memory
Advance Information
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