MC68HC908RK2 Datasheet, PDF (205/232 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
Interrupts
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H and TCH0L)
initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked
channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0 percent duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100 percent duty cycle output. (See 15.9.4 TIM
Channel Status and Control Registers.)
15.6 Interrupts
These TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer counter value changes on
the falling edge of the internal bus clock. The timer overflow flag
(TOF) bit is set when the TIM counter register reaches the modulo
value programmed in the TIM counter modulo register. The TIM
overflow interrupt enable bit, TOIE, enables TIM overflow interrupt
requests. TOF and TOIE are in the TIM status and control
registers.
• TIM channel flag (CH0F) — The CH0F bit is set when an input
capture or output compare occurs on channel. Channel TIM CPU
interrupt requests are controlled by the channel interrupt enable
bit, CH1IE.
15.6.1 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
MC68HC908RK2 — Rev. 4.0
MOTOROLA
Timer Interface Module (TIM)
Advance Information
205