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MC68HC908RK2 Datasheet, PDF (222/232 Pages) Motorola, Inc – Microcontroller Unit
◁
Preliminary Electrical Specifications
16.8 2.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = –1.2 mA)
(ILoad = –2.0 mA)
VOH
VDD –0.3
—
VDD –1.0
—
—
V
—
Output low voltage
(ILoad = 1.2 mA)
(ILoad = 3.0 mA)
(ILoad = 3.0 mA) PTA7–PTA0 only
VOL
—
—
—
—
0.3
1.0
V
—
—
0.3
Input high voltage, all ports, IRQ1, OSC1
VIH
0.7 x VDD
—
VDD + 0.3
V
Input low voltage, all ports, IRQ1, OSC1
VIL
VSS
—
0.3 x VDD
V
VDD supply current
Run(3) (fop= 2.0 MHz)
Wait(4) (fop= 2.0 MHz)
Stop(5)
25 °C
–40 °C to 85 °C
25 °C with LVI enabled
–40 °C to 85 °C with LVI enabled
—
—
2.5
mA
—
—
850
µA
IDD
—
10
—
nA
—
—
100
nA
—
50
—
µA
—
—
350
µA
I/O ports high-impedance leakage current(6)
IIL
—
—
±1
µA
Input current
IIn
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
0
—
200
mV
POR reset voltage(8)
VPOR
0
700
800
mV
POR rise time ramp rate(9)
RPOR
0.02
—
—
V/ms
Monitor mode entry voltage
VHI
VDD+ 2.5
—
8
V
Pullup resistor, PTA6–PTA1, IRQ1
RPU
50
—
120
kΩ
1. Parameters are design targets at VDD = 2.0 ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using internal clock generator module (fop= 2.0 MHz). VDD = 2.0 Vdc. All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. CL = 20 pF. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using internal clock generator module, fOP = 2.0 MHz. All inputs 0.2 V from rail; no dc loads; less than
100 pF on all outputs. CL = 20 pF. OSC2 capacitance linearly affects wait IDD. All ports configured as inputs.
5. Stop IDD measured with no port pins sourcing current, all modules disabled except as noted.
6. Pullups and pulldowns are disabled.
7. Maximum is highest voltage that POR is guaranteed.
8. Maximum is highest voltage that POR is possible.
9. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
Advance Information
222
Preliminary Electrical Specifications
MC68HC908RK2 — Rev. 4.0
MOTOROLA
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