XPC850ZT50BU Datasheet, PDF (59/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

SMC Transparent AC Electrical Specifications
TCLKx
TxDx
(Output)
128
131
133
TENA(RTSx)
(Input)
128
129
130
132
134
RENA(CDx)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 8-55. Ethernet Transmit Timing Diagram
8.8 SMC Transparent AC Electrical Specifications
Figure 8-21 provides the SMC transparent timings as shown in Figure 8-56.
Table 8-21. Serial Management Controller Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
150 SMCLKx clock period ¹
100.00 —
ns
151 SMCLKx width low
50.00
—
ns
151a SMCLKx width high
50.00
—
ns
152 SMCLKx rise/fall time
—
15.00 ns
153 SMTXDx active delay (from SMCLKx falling edge)
10.00 50.00 ns
154 SMRXDx/SMSYNx setup time
20.00
—
ns
155 SMRXDx/SMSYNx hold time
5.00
—
ns
1 _{The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.}
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
59