XPC850ZT50BU Datasheet, PDF (18/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Table 6-6. Bus Operation Timing ¹ (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
Cap Load
FFACT (default Unit
Min Max Min Max Min Max
50 pF)
B34 A[6–31] and D[0–31] to CS valid 3.00 — 6.00 — 4.00 — 0.250 50.00
ns
- as requested by control bit
CST4 in the corresponding word
in the UPM
B34a A[6–31] and D[0–31] to CS valid 8.00 — 13.00 — 11.00 — 0.500 50.00
ns
- as requested by control bit
CST1 in the corresponding word
in the UPM
B34b A[6–31] and D[0–31] to CS valid 13.00 — 21.00 — 17.00 — 0.750 50.00
ns
- as requested by CST2 in the
corresponding word in UPM
B35 A[6–31] to CS valid - as
3.00 — 6.00 — 4.00 — 0.250 50.00
ns
requested by control bit BST4 in
the corresponding word in UPM
B35a A[6–31] and D[0–31] to BS valid 8.00 — 13.00 — 11.00 — 0.500 50.00
ns
- as requested by BST1 in the
corresponding word in the UPM
B35b A[6–31] and D[0–31] to BS valid 13.00 — 21.00 — 17.00 — 0.750 50.00
ns
- as requested by control bit
BST2 in the corresponding word
in the UPM
B36 A[6–31] and D[0–31] to GPL
3.00 — 6.00 — 4.00 — 0.250
50.00
ns
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
B37 UPWAIT valid to CLKOUT falling 6.00 — 6.00 — 6.00 —
—
edge ¹⁰
50.00
ns
B38 CLKOUT falling edge to
UPWAIT valid ¹⁰
1.00 — 1.00 — 1.00 —
—
50.00
ns
B39 AS valid to CLKOUT rising edge 7.00 — 7.00 — 7.00 —
—
11
50.00
ns
B40 A[6–31], TSIZ[0–1], RD/WR,
7.00 — 7.00 — 7.00 —
—
BURST, valid to CLKOUT rising
edge.
B41 TS valid to CLKOUT rising edge 7.00 — 7.00 — 7.00 —
—
(setup time)
B42 CLKOUT rising edge to TS valid 2.00 — 2.00 — 2.00 —
—
(hold time)
B43 AS negation to memory
controller signals negation
— TBD — TBD TBD —
—
50.00
ns
50.00
ns
50.00
ns
50.00
ns
18
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA