XPC850ZT50BU Datasheet, PDF (39/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Table 6-10 shows the debug port timing for the MPC850.
Table 6-10. Debug Port Timing
Num
Characteristic
D61 DSCK cycle time
D62 DSCK clock pulse width
D63 DSCK rise and fall times
D64 DSDI input data setup time
D65 DSDI data hold time
D66 DSCK low to DSDO data valid
D67 DSCK low to DSDO invalid
50 MHz
Min Max
66 MHz
Min Max
80 MHz
Unit
Min Max
60.00 — 91.00 — 75.00 —
ns
25.00 — 38.00 — 31.00 —
ns
0.00 3.00 0.00 3.00 0.00 3.00 ns
8.00
—
8.00
—
8.00
—
ns
5.00
—
5.00
—
5.00
—
ns
0.00 15.00 0.00 15.00 0.00 15.00 ns
0.00 2.00 0.00 2.00 0.00 2.00 ns
Figure 6-29 provides the input timing for the debug port clock.
DSCK
D61
D63
D62
D62
D63
Figure 6-29. Debug Port Clock Input Timing
Figure 6-30 provides the timing for the debug port.
DSCK
DSDI
DSDO
D64
D65
D66
D67
Figure 6-30. Debug Port Timings
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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