XPC850ZT50BU Datasheet, PDF (57/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Ethernet Electrical Specifications
TCLKx
102
TXDx
(Output)
102
101
100
103
RTSx
(Output)
CTSx
(Echo Input)
104
107
104
105
Figure 8-52. HDLC Bus Timing Diagram
8.7 Ethernet Electrical Specifications
Table 8-20 provides the Ethernet timings as shown in Figure 8-53 to Figure 8-55.
Table 8-20. Ethernet Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
120 CLSN width high
40.00
—
ns
121 RCLKx rise/fall time (x = 2, 3 for all specs in this table)
—
15.00
ns
122 RCLKx width low
123 RCLKx clock period ¹
40.00
—
ns
80.00 120.00 ns
124 RXDx setup time
20.00
—
ns
125 RXDx hold time
5.00
—
ns
126 RENA active delay (from RCLKx rising edge of the last data bit) 10.00
—
ns
127 RENA width low
100.00
—
ns
128 TCLKx rise/fall time
—
15.00
ns
129 TCLKx width low
130 TCLKx clock period¹
40.00
—
ns
99.00 101.00 ns
131 TXDx active delay (from TCLKx rising edge)
10.00 50.00
ns
132 TXDx inactive delay (from TCLKx rising edge)
10.00 50.00
ns
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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