XPC850ZT50BU Datasheet, PDF (35/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Figure 6-22 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
IRQx
I39
I40
Figure 6-22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 6-23 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I39
I41
I42
IRQx
I43
I43
Figure 6-23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 6-8 shows the PCMCIA timing for the MPC850.
Table 6-8. PCMCIA Timing
Num
Characteristic
50MHz
Min Max
66MHz
Min Max
80 MHz
FFACTOR Unit
Min Max
P44
A[6–31], REG valid to PCMCIA strobe
asserted. ¹
13.00
—
21.00
—
17.00
—
P45 A[6–31], REG valid to ALE negation.¹ 18.00 — 28.00 — 23.00 —
0.750 ns
1.000 ns
P46 CLKOUT to REG valid
5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P47 CLKOUT to REG Invalid.
6.00 — 9.00 — 7.00 —
0.250 ns
P48 CLKOUT to CE1, CE2 asserted.
5.00 13.00 8.00 16.00 6.00 14.00 0.250
P49 CLKOUT to CE1, CE2 negated.
5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P50
CLKOUT to PCOE, IORD, PCWE, IOWR
assert time.
—
11.00
—
11.00
—
11.00
—
ns
P51
CLKOUT to PCOE, IORD, PCWE, IOWR 2.00 11.00 2.00 11.00 2.00 11.00
negate time.
—
ns
P52 CLKOUT to ALE assert time
5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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