XPC850ZT50BU Datasheet, PDF (58/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Ethernet Electrical Specifications
Table 8-20. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
133 TENA active delay (from TCLKx rising edge)
10.00 50.00
ns
134 TENA inactive delay (from TCLKx rising edge)
138 CLKOUT low to SDACK asserted ²
139 CLKOUT low to SDACK negated ²
10.00 50.00
ns
—
20.00
ns
—
20.00
ns
1 _{The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.}
2 _{SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.}
CLSN(CTSx)
(Input)
120
Figure 8-53. Ethernet Collision Timing Diagram
RCLKx
RXDx
(Input)
RENA(CDx)
(Input)
121
121
124
122
123
Last Bit
125
126
127
Figure 8-54. Ethernet Receive Timing Diagram
58
MPC850 (Rev. A/B/C) Hardware Specifications
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