XPC850ZT50BU Datasheet, PDF (4/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers
(TLBs) and fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512
Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified
little-endian memory systems
— Twenty-six external address lines
• Completely static design (0–80 MHz operation)
• System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC
architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs),
synchronous DRAM (SDRAM), static random-access memory (SRAM),
electrically programmable read-only memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory
interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
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MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA