XPC850ZT50BU Datasheet, PDF (40/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Table 6-11 shows the reset timing for the MPC850.
Table 6-11. Reset Timing
Num
Characteristic
50 MHz
Min Max
66MHz
Min Max
80 MHz
Min Max
FFACTOR Unit
R69 CLKOUT to HRESET high impedance — 20.00 — 20.00 — 20.00
R70 CLKOUT to SRESET high impedance — 20.00 — 20.00 — 20.00
R71 RSTCONF pulse width
340.00 — 515.00 — 425.00 —
R72
—
—
—
—
—
—
R73
Configuration data to HRESET rising
edge set up time
350.00
—
505.00
—
425.00
—
R74
Configuration data to RSTCONF rising
edge set up time
350.00
—
350.00
—
350.00
—
R75
Configuration data hold time after
RSTCONF negation
0.00 — 0.00 — 0.00 —
R76
Configuration data hold time after
HRESET negation
0.00 — 0.00 — 0.00 —
R77
HRESET and RSTCONF asserted to
data out drive
— 25.00 — 25.00 — 25.00
R78
RSTCONF negated to data out high
impedance.
— 25.00 — 25.00 — 25.00
CLKOUT of last rising edge before chip — 25.00 — 25.00 — 25.00
R79 tristates HRESET to data out high
impedance.
R80 DSDI, DSCK set up
60.00 — 90.00 — 75.00 —
R81 DSDI, DSCK hold time
0.00 — 0.00 — 0.00 —
R82
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample
160.00 — 242.00 — 200.00 —
— ns
— ns
17.000 ns
—
15.000 ns
— ns
— ns
— ns
— ns
— ns
— ns
3.000 ns
— ns
8.000 ns
Figure 6-31 shows the reset timing for the data bus configuration.
HRESET
RSTCONF
D[0:31] (IN)
R71
R76
R73
R74
R75
Figure 6-31. Reset Timing—Configuration from Data Bus
40
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA