XPC850ZT50BU Datasheet, PDF (42/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Part VII IEEE 1149.1 Electrical
Specifications
Table 7-12 provides the JTAG timings for the MPC850 as shown in Figure 7-34 to
Figure 7-37.
Table 7-12. JTAG Timing
Num
Characteristic
50 MHz
Min Max
66MHz
Min Max
80 MHz
Unit
Min Max
J82 TCK cycle time
100.00 — 100.00 — 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V
40.00 — 40.00 — 40.00 — ns
J84 TCK rise and fall times
0.00 10.00 0.00 10.00 0.00 10.00 ns
J85 TMS, TDI data setup time
5.00
—
5.00
—
5.00
— ns
J86 TMS, TDI data hold time
25.00 — 25.00 — 25.00 — ns
J87 TCK low to TDO data valid
— 27.00 — 27.00 — 27.00 ns
J88 TCK low to TDO data invalid
0.00
—
0.00
—
0.00
— ns
J89 TCK low to TDO high impedance
— 20.00 — 20.00 — 20.00 ns
J90 TRST assert time
100.00 — 100.00 — 100.00 — ns
J91 TRST setup time to TCK low
40.00 — 40.00 — 40.00 — ns
J92 TCK falling edge to output valid
— 50.00 — 50.00 — 50.00 ns
J93
TCK falling edge to output valid out of high
impedance
— 50.00 — 50.00 — 50.00 ns
J94 TCK falling edge to output high impedance
— 50.00 — 50.00 — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — 50.00 — 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — 50.00 — 50.00 — ns
TCK
J82
J82
J84
J83
J83
J84
Figure 7-34. JTAG Test Clock Input Timing
42
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA