XPC850ZT50BU Datasheet, PDF (3/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Part II Features
Figure 2-1 is a block diagram of the MPC850, showing its major components and the
relationships among those components:
Embedded
MPC8xx
Core
Instruction
Bus
Load/Store
Bus
2-Kbyte
I-Cache
Instruction
MMU
1-Kbyte
D-Cache
Data
MMU
Unified Bus
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Baud Rate Four ^{Interrupt Dual-Port}
Generators ^{Timers Controller}
RAM
Parallel I/O
32-Bit RISC Communications
Ports
Processor (CP) and Program ROM
UTOPIA
(850SR & DSL) Timer
20 Virtual
Serial DMA
Channels
and
2 Virtual
IDMA
Channels
Communications
Processor
Module
Peripheral Bus
SCC2 SCC3 SMC1 SMC2
TDMa
Time Slot Assigner
USB
SPI
I²C
Non-Multiplexed Serial Interface
Figure 2-1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but
without conditional execution
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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