XPC850ZT50BU Datasheet, PDF (55/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

SCC in NMSI Mode Electrical Specifications
8.6 SCC in NMSI Mode Electrical Specifications
Table 8-18 provides the NMSI external clock timing.
Table 8-18. NMSI External Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100 RCLKx and TCLKx frequency ¹ (x = 2, 3 for all specs in this
table)
1/SYNCCLK
— ns
101 RCLKx and TCLKx width low
1/SYNCCLK +5
— ns
102 RCLKx and TCLKx rise/fall time
—
15.00 ns
103 TXDx active delay (from TCLKx falling edge)
0.00
50.00 ns
104 RTSx active/inactive delay (from TCLKx falling edge)
0.00
50.00 ns
105 CTSx setup time to TCLKx rising edge
5.00
— ns
106 RXDx setup time to RCLKx rising edge
107 RXDx hold time from RCLKx rising edge ²
5.00
— ns
5.00
— ns
108 CDx setup time to RCLKx rising edge
5.00
— ns
1 _{The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.}
2 _{Also applies to CD and CTS hold time when they are used as an external sync signal.}
Table 8-19 provides the NMSI internal clock timing.
Table 8-19. NMSI Internal Clock Timing
Num
Characteristic
All Frequencies
Min
Max
100 RCLKx and TCLKx frequency ¹ (x = 2, 3 for all specs in this table) 0.00 SYNCCLK/3
102 RCLKx and TCLKx rise/fall time
—
—
103 TXDx active delay (from TCLKx falling edge)
0.00
30.00
104 RTSx active/inactive delay (from TCLKx falling edge)
0.00
30.00
105 CTSx setup time to TCLKx rising edge
40.00
—
106 RXDx setup time to RCLKx rising edge
107 RXDx hold time from RCLKx rising edge ²
40.00
—
0.00
—
108 CDx setup time to RCLKx rising edge
40.00
—
1 _{The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.}
2 _{Also applies to CD and CTS hold time when they are used as an external sync signals.}
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
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