XPC850ZT50BU Datasheet, PDF (33/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Figure 6-20 provides the timing for the asynchronous external master memory access
controlled by the GPCM.
CLKOUT
B39
AS
B40
A[6:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 6-20. Asynchronous External Master Memory Access Timing (GPCM
Controlled—ACS = 00)
Figure 6-21 provides the timing for the asynchronous external master control signals
negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 6-21. Asynchronous External Master—Control Signals Negation Timing
Table 6-7 provides interrupt timing for the MPC850.
Table 6-7. Interrupt Timing
Num
Characteristic ¹
I39 IRQx valid to CLKOUT rising edge (set up time)
I40 IRQx hold time after CLKOUT.
I41 IRQx pulse width low
I42 IRQx pulse width high
I43 IRQx edge-to-edge time
50 MHz
Min Max
66MHz
Min Max
80 MHz
Unit
Min Max
6.00 — 6.00 — 6.00 — ns
2.00 — 2.00 — 2.00 — ns
3.00 — 3.00 — 3.00 — ns
3.00 — 3.00 — 3.00 — ns
80.00 — 121.0 — 100.0 — ns
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
33