XPC850ZT50BU Datasheet, PDF (36/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Layout Practices
Table 6-8. PCMCIA Timing (continued)
Num
Characteristic
50MHz
Min Max
66MHz
Min Max
80 MHz
FFACTOR Unit
Min Max
P53 CLKOUT to ALE negate time
— 13.00 — 16.00 — 14.00 0.250 ns
P54
PCWE, IOWR negated to D[0–31]
invalid.¹
3.00 — 6.00 — 4.00 —
P55 WAIT_B valid to CLKOUT rising edge.¹ 8.00 — 8.00 — 8.00 —
P56 CLKOUT rising edge to WAIT_B invalid.¹ 2.00 — 2.00 — 2.00 —
0.250 ns
—
ns
—
ns
1 _{PSST = 1. Otherwise add PSST times cycle time.}
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
Figure 6-24 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[6:31]
P46
P45
P47
REG
P48
P49
CE1/CE2
P50
P51
PCOE, IORD
P52
P53
P52
ALE
B18
B19
D[0:31]
Figure 6-24. PCMCIA Access Cycles Timing External Bus Read
36
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA