XPC850ZT50BU Datasheet, PDF (49/76 Pages) Motorola, Inc – Communications Controller Hardware Specifications

Serial Interface AC Electrical Specifications
Table 8-17. SI Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid
35.00
—
ns
(SYNC hold time)
75 L1RSYNC, L1TSYNC rise/fall time
—
15.00
ns
76 L1RXD valid to L1xCLK edge (L1RXD setup time)
17.00
—
ns
77 L1xCLK edge to L1RXD invalid (L1RXD hold time) 13.00
—
ns
78 L1xCLK edge to L1STn valid ⁴
10.00
45.00
ns
78A L1SYNC valid to L1STn valid
10.00
45.00
ns
79 L1xCLK edge to L1STn invalid
10.00
45.00
ns
80 L1xCLK edge to L1TXD valid
80A L1TSYNC valid to L1TXD valid ⁴
10.00
55.00
ns
10.00
55.00
ns
81 L1xCLK edge to L1TXD high impedance
0.00
42.00
ns
82 L1RCLK, L1TCLK frequency (DSC =1)
—
16.00 or
MHz
SYNCCLK/2
83 L1RCLK, L1TCLK width low (DSC =1)
83A L1RCLK, L1TCLK width high (DSC = 1)³
P + 10
—
ns
P + 10
—
ns
84 L1CLK edge to L1CLKO valid (DSC = 1)
85 L1RQ valid before falling edge of L1TSYNC⁴
86 L1GR setup time²
—
1.00
42.00
30.00
—
—
ns
L1TCLK
ns
87 L1GR hold time
42.00
—
ns
88 L1xCLK edge to L1SYNC valid (FSD = 00) CNT =
—
0000, BYT = 0, DSC = 0)
0.00
ns
1 _{The ratio SyncCLK/L1RCLK must be greater than 2.5/1.}
2 _{These specs are valid for IDL mode only.}
3 _{Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.}
4 _{These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,}
whichever is later.
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
49